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 19-0394; Rev 0; 12/97
3-in-1 Silicon Delay Line
_______________General Description
The MXD1013 contains three independent, monolithic, logic-buffered delay lines with delays ranging from 10ns to 200ns. Nominal accuracy is 2ns for a 10ns to 60ns delay, 3% for a 70ns to 100ns delay, and 5% for a 150ns to 200ns delay. Relative to hybrid solutions, these devices offer enhanced performance and higher reliability, and reduce overall cost. Each output can drive up to ten standard 74LS loads. The MXD1013 is available in multiple versions, each offering a different combination of delay times. It comes in the space-saving 8-pin MAX package, as well as a standard 8-pin SO and DIP. It is also offered in industry-standard 16-pin SO and 14-pin DIP packaging, allowing full compatibility with the DS1013 and other delay-line products.
____________________________Features
o Improved Second Source to DS1013 o Available in Space-Saving 8-Pin MAX Package o 20mA Supply Current (vs. Dallas' 40mA) o Low Cost o Three Separate Buffered Delays o Delay Tolerance of 2ns for MXD1013_ _ 010 through MXD1013_ _ 060 o TTL/CMOS-Compatible Logic o Leading- and Trailing-Edge Accuracy o Custom Delays Available
MXD1013
________________________Applications
Clock Synchronization Digital Systems
______________Ordering Information
PART MXD1013C/D_ _ _ MXD1013PA_ _ _ MXD1013PD_ _ _ MXD1013SA_ _ _ MXD1013SE_ _ _ MXD1013UA_ _ _ TEMP. RANGE 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE Dice* 8 Plastic DIP 14 Plastic DIP 8 SO 16 Narrow SO 8 MAX
_________________Pin Configurations
TOP VIEW
IN1 IN2 IN3 1 2 8 7 VCC OUT1 OUT2 OUT3
*Dice are tested at TA = +25C. Note: To complete the ordering information, fill in the blank with the part number extension from the Part Numbers and Delay Times table to indicate the desired delay per output.
MXD1013
3 6 5
___Part Numbers and Delay Times
PART NUMBER EXTENSION (MXD1013_ _ _ ) 010 012 OUTPUT DELAY (ns) 10 12 15 20 25 30 35 40 45 PART NUMBER EXTENSION (MXD1013_ _ _ ) 050 060 070 075 080 090 100 150 200 OUTPUT DELAY (ns) 50 60 70 75 80 90 100 150 200
GND 4
DIP/SO/MAX
IN 1 N.C. IN2 2 3
14 VCC 13 N.C. 12 OUT1
015 020 025 030 035 040 045
N.C. 4 IN3 5 N.C. 6 GND 7
MXD1013
11 N.C. 10 OUT2 9 8 N.C. OUT3
DIP
Pin Configurations continued at end of data sheet.
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.
3-in-1 Silicon Delay Line MXD1013
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.5V to +6V All Other Pins..............................................-0.5V to (VCC + 0.5V) Short-Circuit Output Current (1sec) ....................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.1mW/C above +70C) .......727mW 14-Pin Plastic DIP (derate 10.0mW/C above +70C) ...800mW 8-Pin SO (derate 5.9mW/C above +70C)....................471mW 16-Pin Narrow SO (derate 8.7mW/C above +70C) .....696mW 8-Pin MAX (derate 4.1mW/C above +70C) ...............330mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5.0V 5%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)(Note 1) PARAMETER Supply Voltage Input Voltage High Input Voltage Low Input Leakage Current Active Current Output Current High Output Current Low Input Capacitance SYMBOL VCC VIH VIL IL ICC IOH IOL CIN (Note 2) (Note 2) (Note 2) 0V VIN VCC VCC = 5.25V, period = minimum (Note 3) VCC = 4.75V, VOH = 4.0V VCC = 4.75V, VOL = 0.5V TA = +25C (Note 4) 12 5 10 -1 20 CONDITIONS MIN 4.75 2.2 0.8 1 70 -1 TYP 5.00 MAX 5.25 UNITS V V V A mA mA mA pF
TIMING CHARACTERISTICS
(VCC = +5.0V 5%, TA = +25C, unless otherwise noted.) PARAMETER Input Pulse Width Input-to-Output Delay (leading edge) Input-to-Output Delay (trailing edge) Power-Up Time Period Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: SYMBOL tWI tPLH tPHL tPU (Note 5) 3(tWI) CONDITIONS (Note 5) (Notes 6, 7, 8) (Notes 6, 7, 8) MIN 100% of tPLH TYP MAX UNITS ns ns ns 100 ms ns
See Part Number and Delay Times table See Part Number and Delay Times table
Specifications to -40C are guaranteed by design, not production tested. All voltages referenced to GND. Measured with outputs open. Guaranteed by design. Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling, etc.). VCC = +5V at +25C. Typical delays are accurate on both rising and falling edges within 2ns for delays from 10ns to 60ns, within 3% for delays from 70ns to 100ns, and within 5% for delays from 150ns to 200ns. Note 7: The Part Number and Delay Times table provides typical delays at +25C with VCC = +5V. The delays may shift with temperature and supply variations. The combination of temperature (from +25C to 0C, or +25C to +70C) and supply variation (from 5V to 4.75V, or 5V to 5.25V) could produce an additional typical delay of 1.5ns or 3%, whichever is greater. Note 8: All output delays tend to vary unidirectionally with temperature or supply voltage variations (i.e., if OUT1 slows down, all other outputs also slow down).
2
_______________________________________________________________________________________
3-in-1 Silicon Delay Line
__________________________________________Typical Operating Characteristics
(VCC = +5V, TA = +25C, unless otherwise noted.)
MXD1013_ _100 PERCENT CHANGE IN DELAY vs. TEMPERATURE (OUT1)
MXD1013 TOC01
MXD1013
ACTIVE CURRENT vs. INPUT FREQUENCY
11.0 10.5 10.0 ACTIVE CURRENT (mA) 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 0.0001 0.001 0.01 0.1 1 10 100 INPUT FREQUENCY (MHz) MXD1013_ _075 MXD1013_ _030 ALL INPUTS CONNECTED TOGETHER 0V-3V INPUT NO LOAD 2.0 1.5 % CHANGE IN DELAY 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -40 tPHL tPLH
tPLH tPHL
-20
0
20
40
60
80
100
TEMPERATURE (C)
MXD1013_ _100 PERCENT CHANGE IN DELAY vs. TEMPERATURE (OUT2)
MXD1013 TOC3
MXD1013_ _00 PERCENT CHANGE IN DELAY vs. TEMPERATURE (OUT3)
1.5 % CHANGE IN DELAY 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 tPLH tPHL tPLH tPHL tPLH tPHL
MXD1013 TOC4
2.0 1.5 % CHANGE IN DELAY 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -40 -20 0 20 40 60 80 tPLH tPHL tPHL tPLH
2.0
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
_______________________________________________________________________________________
MXD1013 TOC2
3
3-in-1 Silicon Delay Line MXD1013
______________________________________________________________Pin Description
PIN 8-PIN DIP/SO/MAX 1 2 3 4 5 6 7 8 -- 14-PIN DIP 1 3 5 7 8 10 12 14 2, 4, 6, 9, 11, 13 16-PIN SO 1 4 6 8 9 11 13 16 2, 3, 5, 7, 10, 12, 14, 15 NAME IN1 IN2 IN3 GND OUT3 OUT2 OUT1 VCC N.C. FUNCTION First Independent Input Second Independent Input Third Independent Input Device Ground Third Delayed Output Second Delayed Output First Delayed Output Power-Supply Input Not Connected
_______________Definitions of Terms
Period: The time elapsed between the first pulse's leading edge and the following pulse's leading edge. Pulse Width (t WI): The time elapsed on the pulse between the 1.5V level on the leading edge and the 1.5V level on the trailing edge, or vice versa. Input Rise Time (tRISE): The elapsed time between the 20% and 80% points on the input pulse's leading edge. Input Fall Time (tFALL): The time elapsed between the 80% and 20% points on the input pulse's trailing edge. Time Delay, Rising (tPLH): The time elapsed between the 1.5V level on the input pulse's leading edge and the corresponding output pulse's leading edge. Time Delay, Falling (tPHL): The time elapsed between the 1.5V level on the input pulse's trailing edge and the corresponding output pulse's trailing edge.
____________________Test Conditions
Ambient Temperature: Supply Voltage (VCC): Input Pulse: Source Impedance: Rise and Fall Times: Pulse Width: +25C 5.0V 0.1V High = 3.0V 0.1V Low = 0.0V 0.1V 50 max 3.0ns max 500ns max
Period: 1s Each output is loaded with a 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edges. The time delay due to the 74F04 is subtracted from the measured delay.
4
_______________________________________________________________________________________
3-in-1 Silicon Delay Line MXD1013
TIME INTERVAL COUNTER
PERIOD
tRISE VIH IN VIL 2.4V 1.5V 0.6V
tFALL
PULSE GENERATOR
MXD1013
74F04 TD 50
2.4V 1.5V 0.6V
1.5V
74F04
tWI
PULSE GENERATOR
TD 50
tPHL
tPLH
74F04 PULSE GENERATOR 50 TD
1.5V OUT
1.5V
EACH OUTPUT IS LOADED WITH THE EQUIVALENT OF ONE 74F04. THE DELAY OF THE 74F04 IS SUBTRACTED FROM THE MEASURED DELAY.
Figure 1. Timing Diagram
Figure 2. Test Circuit
__________ Applications Information
Supply and Temperature Effects on Delay
Over the specified range, the MXD1013's delays are typically 2% accurate. Variations in supply voltage may affect the MXD1013's fixed output delays. Supply voltages beyond the specified range may result with larger variations. Although there might be a slight variance in delays over temperature, the MXD1013 is internally compensated to maintain its nominal values.
Board Layout Considerations
Bypass the MXD1013 with a 0.1F capacitor to minimize the impact of high-speed switching on the power supply. The power supply must be able to deliver the required switching currents for proper operation. It is advisable to minimize trace lengths in order to reduce board capacitance as well as the traveling distance between devices. Sockets and wire-wrapped boards increase capacitance and should be avoided.
Loading Effect on Delay Lines
Capacitive loads increase delay times as they increase the rise and fall times of the delay lines. Other logic devices increase the capacitance at the output of the delays, which can affect device performance.
___________________Chip Information
TRANSISTOR COUNT: 824
_______________________________________________________________________________________
5
3-in-1 Silicon Delay Line MXD1013
____Pin Configurations (continued)
TOP VIEW
IN 1 N.C. 2 N.C. 3 IN2 4 N.C. 5 IN3 6 N.C. 7 GND 8 16 VCC 15 N.C. 14 N.C. IN1 TD OUT1
________________Functional Diagram
MXD1013
MXD1013
13 OUT1 12 N.C. 11 OUT2 10 N.C. 9 OUT3 IN3 TD OUT3 IN2 TD OUT2
SO
________________________________________________________Package Information
8LUMAXD.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.


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